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Fixes https://github.com/zachjs/sv2v/issues/270.

I am happy to make changes as needed!

@zachjs Any tips on this? I'd like to have this feature merged soon 😃

Sure! Can you explain why we also add the synthesis attributed? I'll also make some minor tweaks locally.

Can you explain why we also add the synthesis attributed?

From IEC 62142:2005 Section 6.1:

If a synthesis tool supports pragmas to control the structure of the synthesized netlist or to give direction to the synthesis tool, attributes shall be used to convey the required information. The first attribute within the attribute instance shall be synthesis followed by a comma separated list of synthesis-related attributes. Here is the template for specifying such an attribute.

(* synthesis, <attribute=value_or_optional_value>
              { , <attribute=value_or_optional_value> } *)

The attribute synthesis shall be listed as the first attribute in an attribute instance.

NOTE -- By placing the synthesis attribute first, a synthesis tool can more easily parse the attribute instance to determine if the rest of the attributes in the attribute instance are intended for the synthesis tool or for a different tool.

I'm not certain if tools actually require/recognize this though.

I'm confident that Yosys doesn't care about that attribute. Can you check the downstream tools you're using?

I just ran the following example on Vivado v2019.1, Genus 20.11-s111_1, and DC R-2020.09-SP4:

module case_test (int2, int1, int0, irq);
    output int2, int1, int0;
    input [2:0] irq;
    reg int2, int1, int0;

    always @(irq) begin
        {int2, int1, int0} = 3'b0;
        (* parallel_case *)
        casez (irq)
            3'b1??: int2 = 1'b1;
            3'b?1?: int1 = 1'b1;
            3'b??1: int0 = 1'b1;
        endcase
    end
endmodule

Like Yosys, Vivado and Genus are fine leaving off synthesis, (but also work properly if included).

Interestingly, as far as I see, DC does not accept full_case/parallel_case from an attribute at all. It only accepts it as a directive from a comment:

        casez (irq) // synopsys parallel_case
            3'b1??: int2 = 1'b1;
            3'b?1?: int1 = 1'b1;
            3'b??1: int0 = 1'b1;
        endcase

Based on those results, I'll drop the synthesis attribute. Thanks!

Thanks so much!