Scott Nellenbach

Results 38 comments of Scott Nellenbach

RTl code has floating signals for HWRead SWwrite registers causing X's

See issue #65

RTl code has floating signals for HWRead SWwrite registers causing X's

Kamino cloned this issue to [sdnellen/open-register-design-tool](https://github.com/sdnellen/open-register-design-tool/issues/9)

Generate C header file

Hi Prasoon- PR looks like a good addition, however don't think anyone at jnpr is actively working on ordt (since I left a couple years back). At the time I...

Is there an option to enable or disable the flopping of inputs and/or outputs to the RTL generated?

There is currently no switch to disable flopping of primary decoder inputs/outputs - min transaction delay is 2 cycles. Note that this is a minimum when all registers are internal...

External Reset signals Causing RTL generation to fail

Kamino cloned this issue to [sdnellen/open-register-design-tool](https://github.com/sdnellen/open-register-design-tool/issues/18)

External Reset signals Causing RTL generation to fail

See sdnellen fork update - pls submit issues there going forward.

Add support for callbacks to cppmod output

Good feature - lack of field level callbacks seems fine. Submit PR when ready.

Add support for callbacks to cppmod output

Kamino cloned this issue to [sdnellen/open-register-design-tool](https://github.com/sdnellen/open-register-design-tool/issues/2)

How to connect the APB bus to the generated verilog module？

i'd use parallel - should get you very close to what is needed for apb.

How to connect the APB bus to the generated verilog module？

just time - never needed apb specifically. if you provide tested convert logic from parallel to apb, can add it as an option