phdsg vn chfhn

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https://github.com/VCVRack/community/commit/b3a1ca9472bbc6a1e8b86f271ee6faddb6f2328d - updated manifest and submodule.

Updated build.

ok, sounds interesting. have you set this up with modules in a patch? i'm not sure if i understand exactly what you are trying to achieve... yeah. i think only...

so, basically just a bernoulli gate module in front of a counter module like this: ![rainbucket](https://user-images.githubusercontent.com/33329578/36251336-2cbea370-1241-11e8-8c59-754839ed03f2.png)

might (re)look into this at a later time. right now i'm trying to get everything ready to deploy 0.5.8. and then i'll have to prepare the 0.5 -> 0.6 transition....

it's not a bad idea. and it's also not too hard to frankenstein two modules together into one. been doing that a lot. most of the time because certain module...

boy, i see a lot of overlap on module preferences :) here's a preview of the next commit: ![bernswitches](https://user-images.githubusercontent.com/33329578/36278890-81241784-1295-11e8-8363-36bb432de922.png)

yeah that part would be easier on a 4HP panel :) my reasoning was: left = LO / right = HI but i can live with either way, changing with...

guessed so. i only used them with gate signals to make sure it goes 100% B on certain events. up until yesterday. found out that the weird behavior i got...

yeah, my brain is wired a little bit weird when it comes to left/right stuff: i often say left when i mean to say right. in this case i just...