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Published 20 hours ago • verified publisher icon mihir8181
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Metadata

Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.

VerilogHDL-Codes

It includes Synthesizable Verilog Source Codes(DUT), Test-bench and simulation results.

-N Bit ALU

-Clock_Divide_by9

-Counter

-Counter+BCD

-Ripple_Counter_Encoder

-Asynchronous FIFO

-FSM_Mealy

-FSM_Mealy_Using_TASK_for_validation

-FSM_Mealy_Test_Automation_Using_perl

-FSM_Moore

-FSM_Moore_Using_TASK_for_validation

-FSM_Moore_Test_Automation_Using_perl

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verified publisher icon mihir8181

Metadata

Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.

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