Lars Englund

@igrr or anyone that understands igrr:s comment (https://github.com/igrr/esp32-cam-demo/issues/29#issuecomment-307871635): Why does each 32bit i2s sample need to be "padded" with two zero bytes? Why can't we put 4 pixel bytes in...

@igrr Aha, I see, thanks! 16 bit wide hardware limitation makes perfect sense.

I have a couple of pcbs left over that i can send if you pay for shipping..

It's hardware SPI so I don't think it will be interrupted by the WIFI.. but I guess I'll just have to try it :) Yeah, but that's $7 more than...

But the XCLK is first multiplied with the PLL Multiplier (REG_DBLV) before getting divided by the prescaler (2x(REG_CLKRC+1)), so setting REG_DBLV to 4 and REG_CLKRC to 1 should double the...

Perhaps PCLK could be moved to GPIO1 and HREF connected to GPIO2 and start reading pixels when GPIO2 interrupts? Or if all the pixels in a row are read "blindly"...

Let me know how it works out! According to the ATmega328P datasheet it should be able to react in 4 cpu clock cycles. (see [11.7.1. Interrupt Response Time](http://www.atmel.com/Images/Atmel-42735-8-bit-AVR-Microcontroller-ATmega328-328P_Datasheet.pdf)). Looking at...

Cool! Great work! I assume you are doing interlacing in the video? Higher framerate also means reduced artifacts from the rolling shutter (since the time between reading out the first...

Nice, good finds! Have you tried out the RGB444 mode for 15fps color too?

Off-topic: I printed a case for my cam and added a lipo+charger and some infrared LED:s to turn it into a night vision camera for my 4.5yr old son -...