jijingg

I still have publish fail issue on MacOS - sbt : 1.6.2 - OS : Mac-os 12.2.1 - docker-OS: centos7 ``` [warn] You need to remove it from the cache...

> Will this https://codemirror.net/demo/vim.html level of integration be sufficient enough? yes ,this totally enough > I assume there should be an options -> mode switch for someone who is not...

@AlkaidDoge In my experice, most of the situations we can't understand is that we don't have a good understanding of the problem itself. so - First of all, you need...

@bobcladic sorry, the `import spinal.lib.memory.sdram.sdr.IS42x320D` should be imported first . it's fixed now, check the latest commit

@Readon No, not now . show a simple demo wave on browser is ok. but for real IC design project trace wave on browser shold be too hard . on...

@AlkaidDoge check the windows environment variable $PATH, make sure it's clean . https://blog.csdn.net/htgoco/article/details/103940200

@pcesar22 it's have been fixed by change JAVA8, right? the [](https://mybinder.org/v2/gh/jijingg/Spinal-bootcamp/binder) is avaliable now , you can run that online. BTW, `3.3-Spinal-lib-Regif.ipynb` is a new solution for register-bank maybe what...

hi @Readon @Dolu1990 , the FIFO and RAM interface of BusIf have not complete yet. I haven't figured out whether instantiate FIFO to regbank.v Internal or direct output fifo port...

Maybe you can use UInt SInt directly, the UInt/SInt already supports most fixpoint operations. see #233 >Widen a fix point number ```scala val a = SInt(8 bits) val b =...

> Add PhaseInitReg (Init all register uninitiated ) hi @Snoopy87 i have question ,dose this will automatic init all register uninitiated? or just a manually option