jijingg

@Snoopy87, manually option is ok . if you can add report log of uninitiated register it 'will be great . because for some team, they prefer to remove reset on...

@c-thaler good job, i'm not sure should we rename "regif" to "busif", i think the mem mapping and document also need supported later

> 1、The top thing annoying me is that the generated rtl have many "zz" signals, which prevents me making extensive use. I think an elegant rtl is very import，because for...

> sleep mode and test mode @sebastien-riou i agree, some test mode or BIST signal is also a very important topic，In the traditional IC flow, it is usually inserted through...

> One thing i'm not realy for is "val ram = Ram1r1w(MemConfig(32, 256, vendor = vendor))" Perhaps because of my hardware development habits, we want the designer to clearly indicate...

does it better to set `headerWithDate = true` as default , the date is usefull , and do nothing bad , for other pepole they will recognize the generated verilog...

@haritshukla I don't see any substantial benefits of supporting for loops, just the reduction in the number of lines of netlist code. However, this will a great challenge to the...

@ArcheyChen native supoort for Bundle Depending on how you define the drive method, spinal can't help you decide how to drive the bundle. ```scala object palyRGB extends App{ case class...

@ArcheyChen You can refer to this implementation ```scala object FlyWireFromTop{ def apply[T

@jonnykl the right way maybe `x.removeAssignment` instead instead set `x.allowOverride `when your need override . it's more safe ``` // define the signal and set default value val x =...