diffore

Verilog2017 - unpacked array converted as packed

2

Hi, it seems that HdlConvertor does not preserve the dimensions of array when parsing the module interface. See the example below: **example.sv:** ```verilog module test ( logic [0:10] packed_array, logic...

Running on Lenovo Legion Pro 7 16IAX10H. Intel® AI Boost driver: 32.0.100.4404 (2025-10-29) Downloaded from github page: https://public-storage.nexa4ai.com/nexa_sdk/downloads/nexa-cli_windows_x86_64.exe Model from website: [NexaAI/deepSeek-r1-distill-qwen-7B-intel-npu](https://sdk.nexa.ai/model/DeepSeek-R1-Distill-Qwen-7B-Intel-NPU) Runnin with: nexa infer NexaAI/deepSeek-r1-distill-qwen-7B-intel-npu give me: nexa...