algrobman

Other architectures with similar exception/interrupt handling mechanism (PowerPC MSR/SRR0/1 as example) leave "previous" mode/IE state unchanged by Return from Interrupt instructions. Thus nested exceptions/interrupts return CPU to the same state...

Since all CSRs need to be accessed in M-mode and M-mode code can change *XLEN to maximum (DXLEN) why can't all CSRs be defined as current XLEN wide? What is...

Greg, thanks for explanation, however, the CSR width modulation does not explain why the 32bit CSRs can't be defined as 64 (XLEN) bit with upper bits reserved. I don't see...

Again, why can't we redefine the 32bit CSRs as XLEN wide? We have a few privet CSRs with 1- 2 or no bits defined. - Now we have to tell...

> Generally CSRs would be defined to be 32 bits in width if they are expected > to never hold more than 32 bits of fields now and into the...

why the hell only these few CSRs being defined as 32 bit? Why does this even matter, if only way to access the CSR are csrr* instructions, which defined as...

Actually I meant all CSRs, defined as 32 bit registers : fcsr, dcsr,mvendorid, [ms]counteren, mcountinhibit, etc. Now seems because of register abstract command arrsize rules, DM needs a CSR decoder...

RV32ID CPU will need data0,1 registers only. So debugger can understand that XLEN=32, then it reads misa and figures out that it needs to use data0/1 to access FPRs and...

1) 2 data registers and memory abstract command mean 32 bit CPU. 2) 2 data registers and no memory abstract commands mean possibility of 64 bit CPU, failing 64 bit...

bit[7:0] mem[bit[31:0]] is associative array, which can hold up to 4GB data .. it's byte array addressed by 32 bit address.