Ricky Su

Hi @sususjysjy , may I know your use case of adding riscv-toolchain to Vitis IDE? Currently we don't provide this feature but if you can share more details maybe we...

Hi @nhkrishna , please check whether the following articles are helpful: - https://docs.xilinx.com/r/en-US/ug1076-ai-engine-environment/Profiling-Graph-Latency - https://github.com/Xilinx/Vitis-Tutorials/blob/2022.2/AI_Engine_Development/Feature_Tutorials/09-debug-walkthrough/Debug6_pr.md - https://github.com/Xilinx/Vitis-Tutorials/blob/2022.2/AI_Engine_Development/Feature_Tutorials/09-debug-walkthrough/Debug4_et.md#Number-of-event-trace-streams-methodology cc @JithinPillai

@FredKellerman Thanks for submitting this PR. We will verify and merge.

@AnusheelXilinx could you review and test? Thanks.

Hi @xflorentw , could you check the command `set_property CONFIG.REMAPS {{M00_AXI {{0x4000_0000 0x200_0000_0000 1G}}}} [get_bd_intf_pins /ps_noc/S01_AXI]` and make sure the pin name matches Vivado example? The Vivado example design may...

Hi @SURUTHI1605 , could you help with this quesiton?

Hi @Rampagee , could you help with this issue?

Hi @hanghug , is this issue related to a specific tutorial? If so, could you point out the tutorial link? If not, could you please direct to forums.xilinx.com for tech...

Hi @OTremois , could you help with this question? In the error log, it shows the following: ``` INFO: [v++ 60-2256] Packaging for hardware ERROR: [v++ 60-2254] File specified by...

Hi @belanasaikiran , may I know in which tutorial and step this issue occurs?