Philipp Wagner

Add a "currentmodule" directive to avoid nesting

1

I want to document a module (in this case, https://github.com/lowRISC/ibex/blob/master/rtl/ibex_core.sv). This module has a fair amount of ports and parameters, the current documentation can be found at https://ibex-core.readthedocs.io/en/latest/integration.html. When trying...

It looks like the type parser isn't able to parse enum types in parameter declarations. Failing rST code: ```rst .. verilog:parameter:: parameter ibex_pkg::regfile_e RegFile = RegFileFF Register file implementation select:...

stable/1.9 backports (part 2)

1

Another set of stable/1.9 backports. - **Add support for timescale and wave dumping in Icarus Verilog runner** - **runner: Fix generating FST files on Windows when using Icarus** - **Fix...

VPI: Explore always using vpiNoDelay

14

Currently we're using vpiInertialDelay to set signals (except for strings). vpiNoDelay could be more appropriate, but doesn't work currently. Explore if switching makes sense, and what roadblocks we might hit....

CI: mingw fails to compile Icarus Verilog and hangs after "mkdir dep"

3

Currently, Windows CI fails to compile Icarus Verilog; since the job times out: ``` Wed, 28 Feb 2024 18:57:22 GMT g++ -shared -Wl,--enable-auto-image-base -o sizer.tgt sizer.o scan_lpms.o scan_logs.o -L.. -livl...

Easier LibreCores CI Slave Setup

7

## Overall Goal For LibreCores CI, we want to give users the ability to easily hook their machines into the CI system to run CI _on their own project_. ##...

Support Questa qrun/QIS flow

26

Support the qrun/QIS flow in Questa in the Makefile flow Closes #4364. v2 from https://github.com/cocotb/cocotb/pull/3274: - Default to the new flow from Questa 2023.1 on (the first version which includes...

Riviera: Crash when setting all members of a packed struct in one write

2

Attempting to set all data members in packed struct with a single VPI write crashes Riviera-PRO 2024.04. cocotb testcase `test_struct.test_packed_struct_setting` ```systemverilog // tests/designs/sample_module/sample_module.sv (simplified) typedef struct packed { logic val_a;...

For a SystemVerilog module port, Riviera-PRO 2024.04 returns `vpiStructNet` with `vpiPacked` always set (it seems), even if the struct is unpacked. ## Background In #3587, support for structs and unions...

Increase DNS timeout for `dsc server:deploy`

2

### Describe the bug When I run `dsc server:deploy` I am getting a DNS resolution failure in the "Plugin Registry pod bootstrap" step. The DNS records are created and the...