Philipp Wagner
Philipp Wagner
It seems that objcopy has a "verilog" target option which creates vmem files. See if that option works for us and remove bin2vmem in this case.
Our example design `compute_tile_sim` currently fails the Verilator lint. Some lint warnings seem to be bogus, but are hiding the important ones. 1. Find a way to suppress the warnings...
Eclipse is a rather nice choice for working on OpTiMSoC as it is able to support different languages through plugins with advanced features like auto-complete and syntax checking. However, currently...
When sending a message in which one data item is a negative number the `optimsoc_mp_msg_recv()` function never returns. Sending a message with a positive number in it is received. The...
Currently MAM is inserted into the memory path in a rather "hackish" way. We should make the MAM a normal master on the bus. @wallento I think you already have...
The data is available (inside LIS) at /nfs/projects/optimsoc/aramis/
For demos and evaluations we'd like to have a communication channel between the host and the compute resources in optimsoc. A couple possible solutions: 1. Build a bridge between the...
Verilator reports multiple combinatorial loops, many of them going through the network adapter and message passing units. @wallento do you have had a look at these before or do you...
Currently we rather bad resource utilization after placement in the example system_2x2_cccc design for the Nexys 4 DDR board. For example, a design which makes use of 66 % of...
The development documentation (https://optimsoc.org/docs/master/user_guide/develop.html) is not explicit enough about using optimsoc and the examples from the same git tag. Figure out how to document this better (or automatically check somehow).