ijor
ijor
Hi everybody, @jotego @a1exh As far as I can see the bugs are not in the original code. @fredrequin I need to review the changes before accepting the pull request....
@fredrequin On exactly which FPGA model and with which Quartus version you got those size and performance results?
Hi gyurco, Sorry for the delay, but please bear with me, I need to check it thoroughly before merging your patch.
> @ijor could you make a progress with the check? > As without enabling the BRAM option, it doesn't change any behavior, it should be perfectly safe. The ugliness of...
Hi udif, Interesting, I wasn't aware about that System Verilog specification. Thanks for letting me know. So more than a simulator bug it indeed seems to be a SV quirk....
> By the standard, SYNTHESIS is predefined for all synthesis tools: Doesn't seem so. Quartus, at least some versions, doesn't support this.
Unfortunately it really doesn't matter here, if it is, or it was, a standard feature. As long as Quartus doesn't support this, I am afraid I cannot use it.
Yes, it's a typo, the ~SRMC_RES operand shouldn't be there at all. But it is harmless because the value doesn't alter the condition.