Henner Zeller
Henner Zeller
Thanks! We also already have set up a homebrew repo, but it needs to have some triggering enabled so that we can automatically build a new release there: https://github.com/chipsalliance/homebrew-verible ......
the CI now ran, but it had some trouble in running the MacOS build, can you have a look ?
BTW, for finding some interesting examples and 'good to evil' uses of the verilog preprocessor, always good to have a look at Wilson's paper https://veripool.org/papers/Preproc_Good_Evil_SNUGBos10_paper.pdf It might give some ideas...
Possibly because it is allowed to have some [`$systemfunctions` without calling parenthesis](https://github.com/chipsalliance/verible/blob/master/verilog/parser/verilog.y#L7753-L7754).
Also cc @fangism
There are two ways that you can make the current version of Verible do this. Either by suppling a comment telling it to skip formatting for some lines ```verilog logic...
CC @mglb (who did a lot of formatting work) I think it might be a good idea to have some alignment of expressions, maybe if they are parenthesized. So if...
@mglb @tgorochowik (and maybe @fangism ): can you help @pinkcatfly find the right place to get started ?
I don't have access to a Windows machine, but I'll try to reproduce this on a Linux machine (so far I have only tested the language server successfullywith emacs, vscode,...
You can run your test with ``` bazel test //verilog/analysis/checkers:explicit_begin_rule_test ```