HS

My interest is primarily in the Verilog and SystemVerilog parsers. I intend to use it for building a verification tool. But I need a synthesizable netlist and that would need...

Would it be too much of an ask to finish the parser work independently of whether or not it is Python compatible?

> could you disclose your file or reproduce a testcase that you can attach to a new issue ? Created Issue #98

> @mewais is now working on elaboration (as a hobby project) Does this extend to inferencing?

@mewais By inferencing I meant identifying higher level constructs like flip-flops, inverters, etc. From your answer, it doesn't look like that is in your plan for now. This functionality is...

> I guess #88 and #89 are the same. I consider them different. #88 is a bug (parsed values aren't propagated correctly) whereas #89 is a missing feature (nothing in...

No that doesn't work because to build static libs ```HDLCONVERTOR_PYTHON``` has to be defined and that brings in dependency on Python. Moreover, hdlConverter/CMakeLists.txt has an explicit dependency on Cython and...

We are building for Windows, Linux (multiple different flavors) and Mac, so we need for all these platforms. That said, I don't expect you to support all these platforms. If...

The precompiled header changes was merged and reverted again. It's not part of the current master. Change that introduced it - https://github.com/chipsalliance/UHDM/pull/550 Change that reverted it again - https://github.com/chipsalliance/UHDM/pull/552 If...

A little context here would have helped. My bad. This issue came up because one of team member is attempting to get a `language server` working and he has a...