Hoa Nguyen

I don't know if those stats count accesses from speculative instructions. If that's the case then we should move this to the execute stage. If not, this change looks good...

That's great!

Hi @Ye-Jinhong, can you elaborate the issue more? (i.e., what was the unexpected output for c.jal/c.jalr?)

I see. If I'm not mistaken, that's a bug. Interestingly, gem5 O3CPU does jump to the correct location due to branch prediction mechanism [1]. This is because c_jr's and c_jalr's...

@Ye-Jinhong can you make a PR that fixes this?

I still think we need to have the assertion `mode == state->mode` without the `||`. However, I'm okay with this if it means this change allows clflush to work.

Is there a plan to merge this to v24.0 release?

There's currently no active refactoring of the riscv address translation that I'm aware of. Making gem5 work with sv48 is probably straightforward, but ideally, gem5 should allow users to choose...