hello-eternity
hello-eternity
I meet some error when using conda-eda which uses the python script in this repo, could I issue here? The error is cause by scripts/extract_antenna_count.py, when Fastrouitng stage. The test...
The error log is like this when running the python inference.py --config configs/inference.yaml --video_source=./docs/demo/videos/RD_Radio34_003_512.mp4 --image_source=./docs/demo/images/100.jpg --cross_id --output_dir=./docs/demo/output ``` Load pre-trained e4e Encoder from checkpoints/Encoder_e4e.pth done. Load pre-trained hfgi encoder from...
让他执行一些长文本输出的时候会报这个错误，怎样让code等待更久的时间，retry 1 times, error: TypeError: fetch failed
I use little about ts, can you give me a basic info about how to get new users info,I want to use python to implement this query process.
I got an error like the title. The detailed error information is like this `ERROR: /root/yosys-uhdm-plugin-integration/UHDM-integration-tests/tests/orv64/rtl/common/pygmy_func.sv:24: Encountered unhandled object '' of type 'break_stmt'` The source code is : ``` for...
I would like to translate the sv code of orv64 [(https://gitlab.com/picorio/OpenSource/hardware/orv64)](url) into verilog code and use yosys to synthesis it. and I meet some error uhdm can't find width for...
I use the latest uhdm to run this orv64 code and encounter segementation fault without more information  This is the test case [https://github.com/hello-eternity/test_orv64_uhdm/tree/main](https://github.com/hello-eternity/test_orv64_uhdm/tree/main) In the Makefile.in , $(TEST_DIR) need...
The full error is `ERROR: /root/yosys-uhdm-plugin-integration/UHDM-integration-tests/tests/orv64/subproj/es1y/rtl_gen/pygmy_intf_typedef.sv:147: Encountered unhandled typespec in process_typespec_member: 'orv64_access_type_t' of type 'unsupported_typespec'` the source code definition is ``` typedef struct packed { orv64_vpn_t req_vpn; orv64_access_type_t req_access_type; }...
I use the uhdm to translate the orv64 SystemVerilog file into the verilog file, and want to do synthesis by yosys, the orv64 gitlab adress is here: [https://gitlab.com/picorio/OpenSource/hardware/orv64](url) But there...
As the title error I would like to translate the sv code of orv64 into verilog code and use yosys to synthesis .[orv64](https://gitlab.com/picorio/OpenSource/hardware/orv64) `/root/yosys-uhdm-plugin-integration/UHDM-integration-tests/tests/orv64_uhdm/rtl/../rtl/orv64/orv64_ptw_core.sv:224: ERROR: 2nd expression of procedural for-loop...