Harvard Architecture, Circuits, and Compilers

SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin

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A pre-RTL, power-performance model for fixed-function accelerators

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http://vlsiarch.eecs.harvard.edu/research/recommendation/

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HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference

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FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks

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End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.

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An LLVM pass to profile dynamic LLVM IR instructions and runtime values

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