Hao

`csrc` instr get wrong `mstatus` value

1

### Before start - [X] I have read the [RISC-V ISA Manual](https://github.com/riscv/riscv-isa-manual) and this is not a RISC-V ISA question. 我已经阅读过 RISC-V 指令集手册，这不是一个指令集本身的问题。 - [X] I have read the [XiangShan...

Add `riscv64-unknown-elf-` as `CPT_CROSS_COMPILE` when `riscv64-unknown-linux-gnu-` does not exist.

[Bug Report] `mie` register not implemented correctly

3

According to the privileged [specification](https://riscv.org/technical/specifications/) in chapter **3.1.9. Machine Interrupt Registers**, some bits in MIE are set to zero.  However, if we write `0xffffffff` to `mie`, the NEMU will...

`mtval` different

1

### Before start - [x] I have read the [RISC-V ISA Manual](https://github.com/riscv/riscv-isa-manual) and this is not a RISC-V ISA question. 我已经阅读过 RISC-V 指令集手册，这不是一个指令集本身的问题。 - [x] I have read the [XiangShan...

`mcause` is different between xiangshan and spike when execute `sh`.

9

I have tested it in **the newest version**, it works! No more `mstatus` different for now. However, this test case raise `mcause` different: ``` sh s2, 1259(s0) # test case...

Xiangshan does not throw IAF trap

5

### Before start - [x] I have read the [RISC-V ISA Manual](https://github.com/riscv/riscv-isa-manual) and this is not a RISC-V ISA question. 我已经阅读过 RISC-V 指令集手册，这不是一个指令集本身的问题。 - [x] I have read the [XiangShan...

How reliable is the reference model of cosim?

2

I installed the co-simulation system, followed this [tutorial](https://ibex-core.readthedocs.io/en/latest/03_reference/cosim.html#setup-and-usage) to install cosim and tested it on ibex. One of the test cases shows unexpected behavior: ``` FAILURE: Co-simulation mismatch at time...

Writing `mseccfg`=0x1 will jump to `_vectors_start`

6

## Observed Behavior When write 0x01 to `mseccfg`(0x747), some unknown behavior happened: ibex jump to `_vectors_start`. I have tested some values, when we write 0x4 or 0x8, ibex is normal,...

Our fuzzing methodology uncovered anomalous behavior in the Rocket [f517abb](https://github.com/chipsalliance/rocket-chip/commit/f517abb), using Spike as the reference model. **Test Case Description:** At `pc = 0x80000054,` the `mepc` is `0x8000005e`, which corresponds to...

Our fuzzing methodology uncovered anomalous behavior in the BOOM v3 processor, using Spike as the reference model. **Test Case Description**: At `pc = 0x80000054`, the `mepc` is `0x8000005e,` which corresponds...