Graeme Smecher
Graeme Smecher
It looks like hdlparse learned how to be case insensitive for VHDL code in 2018 (https://github.com/kevinpt/hdlparse/commits/master/hdlparse/vhdl_parser.py), but this version hasn't yet made it out to PyPI (https://pypi.org/project/hdlparse/). Can you please...
I'm using smcroute on a number of embedded boards, each of which forwards multicast data from a private source interface to a single multicast destination on a shared subnet. Because...
This issue is a bug in the underlying XSI implementation (in at least Vivado 2021.2). It's being tracked here to inform pyxsi users. A testbench that instantiates multiple simulator snapshots...
This simplifies call sites in pm.cpp, and avoids a number of assumptions about arrays being allocated with the correct sizes. I am not a C++ guru, but I believe this...
Currently, pass/stopbands are specified using std::vectors for frequency, amplitude, and weight. In principle, this allows arbitrary FIRs to be constructed using a very high number of subbands. However, it doesn't...
This is an updated version of #153, and should clear up https://github.com/tenox7/ttyplot/issues/53 and https://github.com/tenox7/ttyplot/issues/22. This is a quick and possibly rough implementation - comments welcome. The rebase looks clean enough,...
In the following documentation section: https://github.com/riscv-software-src/riscof/blob/69b57e14a01b8e1eb5249ca757f3d08a1a6e2c72/docs/source/installation.rst#cloning-the-architectural-tests ...the command $ riscof --verbose info arch-tests --clone should be $ riscof --verbose info arch-test --clone (without the plural on "arch-test")
On RV32IC architectures, the SAIL model currently fails with the following messages: ``` /path/to/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-beq-01.S: Assembler messages: /path/to/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-beq-01.S:26: Error: unrecognized opcode `fence.i', extension `zifencei' required /path/to/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-beq-01.S:43: Error: unrecognized opcode `fence.i', extension...
Most of the RFDC API is symmetric - for every Set(...) there is a corresponding Get(...) call. `XRFdc_SetDACVOP()` has no corresponding `XRFdc_GetDACVOP()` call. Please consider adding it.
### Problem 1: device tree mismatch in embeddedsw The rfdc driver expects a device tree with most of the configuration tucked into a "param-list" entry, as can be seen [here](https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/rfdc/src/xrfdc_sinit.c#LL150C1-L152C1):...