Graeme Smecher

@xobs, @mithro - it's not the Verilog rewrite that's the stumbling block (though I am happy to see it - the closer the two codebases are, the happier I am...

@xobs - that's amazing. Are you working towards a PR here? Either way - you have cleared the hurdle and merging your work is a clear net benefit. I am...

Also: two questions about the equivalence checking you've been using. - Is the machinery included in open-source yosys without commercial dependencies, and hence suitable for CICD? - Is it hassle-free...

Fantastic - I am looking forward to seeing the macro-based design crashland. (I am assuming it's most useful to stay out of your way here.) For the time being, VHDL...

@xobs, this makes me deliriously happy. Two drive-by questions: - How will you load code (microcode and program code) into this? I'm used to pre-loading BRAM contents on an FPGA,...

Zcb's C.SB and C.SH instructions are now implemented in #8, as a means of emulating 32-bit SB/SH.

Oops, I see this is already discussed in #59. It looks like there are some options: 1. Homogeneous typed arrays per RFC 8746 2. Classic CBOR arrays with individual type...

Note we've got an out-of-tree implementation here: https://github.com/gsmecher/tuberd/blob/master/tuber/codecs.py It's BSD 3-clause - if there's any ambiguity about whether you can borrow code I'm happy to chase down the contributor and...

Bandwidth is a terribly scarce resource. :) Thanks for all of your work.