VerilogLanguageExtension
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gojimmypi
Verilog Language Extension for Visual Studio
for example [picorv32.v line 433](https://github.com/gojimmypi/VerilogLanguageExtension/blob/master/TestFiles/picorv32.v.txt#L433) 
should not need to press any keys at initial file load time to force redraw for proper highlighting
per review: Need to add support for: ``` wire signed yxz; ``` xyz ends up not being recognized as a wire. It's the "signed" keyword that confuses it.
declarations inside of one module are note properly scoped for hover text definitions where there is more than one module defined in a given file with the same-named variable. For...