4o

where do i start if i were to implement active-low reset?

https://github.com/nmigen/nmigen/blob/818c8bc46485ada0f31ad8ec23182ad01a6c7da1/nmigen/back/rtlil.py#L994 looks promissing. fixing this for negedge produces ```vhdl sync negedge \rst update \v \v$next ``` in rtlil (look ok so far, is it a valid active-low reset in rtlil?)....

can't find explicit confirmation that rtlil supports `negedge` SyncRules, but yosys source annotation says `negedge` is a valid type for SyncRule: http://eddiehung.github.io/yosys/d3/dc3/namespaceRTLIL.html#a79713e13c00e4e216c60fb297be1900f update: quick tests show that `sync negedge \rst`...

my group has been using this approach for years cause we run our testbenches for both rtl and post-synthesis netlists. so the first things i did with nmigen is: 1....