Gergő Érdi

https://github.com/gergoerdi/clash-chip8 is my CHIP-8 implementation targeting FPGAs, implemented in Clash

Uncurried BiSignalIn params lead to faulty Verilog

8

``` module Bi (topEntity) where import Clash.Prelude import Clash.Annotations.TH topEntity :: "CLK_50MHZ" ::: Clock System -> "RESET" ::: Reset System -> ( "SCL" ::: BiSignalIn 'PullUp System (BitSize Bit) ,...

Wrong port name annotations for nested tuples

2

``` module Bug (topEntity) where import Clash.Prelude import Clash.Annotations.TH topEntity :: "clk" ::: Clock System -> Signal System ( "a" ::: Bit , ( "x" ::: ("u" ::: Bit, "v"...

Generated VHDL/Verilog crashes Xilinx ISE 14.7

15

I am getting the following error from the Xilinx ISE consuming CLaSH-generated VHDL: > Line 6134: Signal `inst_chip8/clash_explicit_mealy_mealy_cpuout/_` is defined more than once. I don't have any idea on how...

BRAM initializers use loops in initial block, triggering "maximum iteration" counters in synthesizers

16

The simplest possible block RAM, one that is initialized to all zeroes: ``` import Clash.Prelude type Addr = Unsigned 13 type Value = Unsigned 8 topEntity :: Clock System Source...

Bad performance when pattern-matching bit by bit

12

Please find a full standalone compilable code at the end of this post. I am experiencing very bad scaling from the CLaSH synthesizer when it is compiling the instruction fetch/decode...

Sudden explosion in inlining depth needed

3

Summary: I have some CLaSH code where if I start using some seemingly innocent, non-recursive utility function, suddenly the inlining limit required to synthesize it shoots up through the roof....

Type-directed recursion fails to synthesize

7

In the following minimalized example, `sumSucc` is recursive over the type-level index `ns` (via a little indirection in the `KnownNats` typeclass). Even though the types completely drive the recursion, i.e....

Xargo doesn't respect `rustc` path set in `.cargo/config`

4

I have a local `.cargo/config` file which sets the path to `rustc`: ``` $ cat .cargo/config [build] rustc = "/home/cactus/prog/rust/rust-avr/build/build/x86_64-unknown-linux-gnu/stage1/bin/rustc" target = "avr-atmega328p.json" ``` It seems that Xargo doesn't pick...

Stack installation files missing, Docker image is huge and unwieldy to use

1

There are currently two [documented](https://asterius.netlify.app/) ways of installing `ghc-asterius`: * [Using a prebuilt container](https://asterius.netlify.app/images.html) * [Using Stack](https://asterius.netlify.app/building.html) Both of these have problems: * The Docker image contains a LOT more...