Gergő Érdi

Unfortunately, `fasm2bels` fails on the resulting `.fasm` file, [as reported here](https://github.com/SymbiFlow/symbiflow-xc-fasm2bels/issues/76#issuecomment-945314061).

Yes, the example crucially depends on the convoluted way of one-hot-encoding `i` into `result`. The code is simplified from Clash output. It could be that the Verilog is wonky, but...

I'm not sure why `idx` goes from `0001` to `1110` instead of `0010`, can you elaborate on that? Nevertheless, I'm afraid I might have simplified the code beyond relevance, if...

Out of curiosity, I tried extending `part.hpp`: ``` diff --git a/src/part.hpp b/src/part.hpp index 1c02fdf..af3198e 100644 --- a/src/part.hpp +++ b/src/part.hpp @@ -85,6 +85,7 @@ static std::map fpga_list = { {0x02d020dd, {"altera",...

Could it be that I created my `.svf` file incorrectly? ``` $ quartus_cpf -c -n p -g 3.3 -q 24MHz Top.sof Top.svf ```

I didn't know SVF upload was supposed to be slow! I killed it after 1 or 2 seconds because that's how long it took to upload the original `.sof` file...

Let me know if I can help -- e.g. by attaching the `.sof` or `.svf` file, running a special version of `openFPGALoader` with the board with loads of extra debug...

[ArrowDECA-bitstreams.zip](https://github.com/trabucayre/openFPGALoader/files/8531547/ArrowDECA-bitstreams.zip)

I'm happy to try your suggestion, except I have no idea what `defadvice` is :) Can you provide more detail on what exactly I should try?

> Also, I think you noticed, but I hid the `Var` constructor so that users are forced to use `var`, then I can use some logic inside my DSL monad...