ganghuang

Support feedthroughs/non-ANSI complex ports (IEEE 1800-2017 23.2.2.1)

8

It seems the current version of verilator doesn't support module like this: ``` module via (.a(w), .b(w)); inout w; wire w; endmodule ``` There was a discussion https://forums.xilinx.com/t5/Welcome-Join/synthesizable-verilog-connecting-inout-pins/td-p/284628 And as...

parameter with quotation marks "TRUE" "FALSE" in python

3

I just installed the svinst from `pip install svinst` and want to try it with a simple module like this: a.sv ``` module t1 #(parameter P="TRUE")(); reg a=0; b #(.P(P))b1(.a(a));...

Nano every reset

3

I can not get the nano every reset by sending the 1200 baud signal and I am thinking this might because of the atsamd11d14a is not doing that. I noticed...