g2gps

Just to elaborate. Our end goal is to be able to debug our application using litex_sim and the vexriscv_smp soft core. Is that something which is currently feasible? I've noticed...

Thanks @enjoy-digital. `litex_server` now connects initially, but fails once openocd attempts to connect. My workflow: litex_sim ``` litex_sim --integrated-main-ram-size=0x10000000 --cpu-type=vexriscv --cpu-variant=standard+debug --ram-init=nuttx.bin --csr-csv=csr.csv --with-ethernet --with-etherbone --sim-debug # Output as in...

@Dolu1990 Yes. The overall goal would to be able to use gdb to debug, using the VexRiscv-SMP core, with MMU enabled.

I was able to test this out on the ESP32-C3 devkitc, same issue: ``` ESP-ROM:esp32c3-api1-20210207 Build:Feb 7 2021 rst:0x1 (POWERON),boot:0xc (SPI_FAST_FLASH_BOOT) SPIWP:0xee mode:DIO, clock div:1 load:0x3fcd5820,len:0x16c0 load:0x403cc710,len:0x87c load:0x403ce710,len:0x2f54 entry 0x403cc710...

Thanks acassis, I just tried this out with the `esp32c3-devkit:tickles` configuration with, - CONFIG_RR_INTERVAL=0 (The default for this configuration) - CONFIG_RR_INTERVAL=20 - CONFIG_RR_INTERVAL=200 In each case, I get a similar...

I retested this today with NuttX main. The issue is not present with `qemu-armv8a:nsh_smp_tickless`. Although I still have the same failed result with the `esp32c3-devkit:tickless` and Litex based configuration. If...

I've added a branch to our fork of nuttx-apps (https://github.com/motec-research/nuttx-apps/tree/issues/11189) and nuttx (https://github.com/motec-research/incubator-nuttx/tree/issues/11189). With the example program and configuration added. Hopefully it makes trying this out a bit easier.

I've found the cause of the issue. Both `esp32c3` and the Litex port use the simple interval timer for tickless events. If I change the tickless implementation to support `CONFIG_SCHED_TICKLESS_ALARM`,...