Mireille

Thanks for all the tests! I hope I can find some energy soon to finish my prefetch buffer rewrite and look at all the new tests.

Thanks for this! I'll definitely try to work on this soon. I noticed that your readme says `Tests prefetcher behaviour when branching to nearby addresses`. Did you by chance happen...

I can check my notes and test ROM tomorrow or on the weekend. It's been a while and I don't remember the details anymore.

Thanks for this! Looks like I had an oversight regarding the APU master enable bit in 16-bit and 32-bit IO handlers. Regarding fixed source ROM DMA: that's odd. My impression...

This is really weird. I wrote some tests for DMA1-3 decrementing and fixed ROM source DMAs and they all seem to indicate that a single non-sequential + N sequential accesses...

I have messed around with your test a bit and noticed that there appears to be a missing comparison for the `tmr_read_b` value around here: ```asm adr r5, .tmr_read_b ldr...

I have started to test FIFO DMA specifically a bit and noticed that my test sometimes seems to lock up on hardware when timer overflows happen during a FIFO DMA...

Thanks for this! Could you quickly tell me what version of NanoBoyAdvance you used to create the savestates? Thanks.

Sorry, at the moment this is not possible!

Could you retest the game with the latest [development build](https://nightly.link/nba-emu/NanoBoyAdvance/workflows/build/master) please? I just pushed some fixes to the envelope volume calculations which might affect this game.