Andy

Timing issue if for startWrite, if not using an external clock

1

In RF24::startWrite, there is a coded delay of 15us after power up. This time is in the data sheet as Tpd2stby and only valid for chips using an external clock....

I use this for testing and needed the ability to see a history of pages to check interleaving. This adds the ability so that the user can request that `ant.py`...