hackt

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We need to generate the verilog and spice testbenches for prsim-verilog-spice cosimulation for Synopsys VCS and Cadence Incisive. For example, if we have the following files: test.prs: ``` import "source.prs";...

nbingham1

hacprsim false positive error on channel connections

1

export defchan ev1of2 _ch_e- _ch_e => ch.f- _ch_e | ~_ch_e -> ch.t- } ch.v = ch.f; } source dut; prsim> channel dut.ch ev:0 :0 d:2 Channel acknowledge is not allowed...

nbingham1

most of the work for this is renaming files/extension under test/prsim/vpi. update any necessary documentation too.

fangism

when running spice-verilog-prsim cosimulation, all variations of $prsim_cmd("timing random") will hang.

nbingham1

It looks like you forgot to implement watchall-values

nbingham1

feature request for compile time assert to print message

1

spec { assert() } needs to be able to print a given message. Maybe like this? spec { assert() }

nbingham1

hacprsim channel-clocked no support for reset data value

1

clocked channel sources are the best option to test logic trees, but when testing c-element trees, I need to be able to provide a reset value. Current workaround is as...

nbingham1

hacprsim coredump on using implicit sources

1

export defproc test(bool x) { prs { !Vdd -> x- } } test dut; hacprsim: ../../src/sim/prsim/State-prsim.cc:622: void HAC::SIM::PRSIM::State::__initialize(const bool): Assertion `time_traits::is_zero(current_time)' failed. Aborted (core dumped)

nbingham1

# Scratchpad - 1: WISHLIST: time-travel/time-warp debugging in hacprsim Considering extending an interactive mode that allows one to jump to any point in time, in the history of a prsim...

joydip15

The command is registered in hacprsim as `no-status-interfere` but documented as `no-status-interference`. Same with the `no-status-weak-interfere` command documented as `no-status-weak-interference`.

fangism