script for generating co-simulation (verilog/spice) testbench files from a DUT in HAC source

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We need to generate the verilog and spice testbenches for prsim-verilog-spice cosimulation for Synopsys VCS and Cadence Incisive. For example, if we have the following files:

test.prs:

import "source.prs";
import "sink.prs";
import "buffer.prs";

globals g;
e1of2 L, R;
source_random_e1of2 Lsrc(g, L);
sink_e1of2 Rsink(g, R);
wchb dut(g, L, R);

test.prsimrc

set g._sReset 0
set g._pReset 0
cycle
set g._pReset 1
cycle
set g._sReset 1
cycle

Then we can make the following call to prspice:

prspice -c netgen.conf -i 'dut' -tool 'incisive' test.prs test.prsimrc

where 'i' stands for instance 'c' stands for configuration and 'tool' picks the verilog/spice tool flow being used, and it will generate the toplevel verilog and spice test benches, create a netlist for the dut, create a prso for the environment, and create a Makefile with the commands necessary to run the simulation.