Fabian Schuiki
Fabian Schuiki
The comb dialect is missing folds for the new SV case equality and wildcard equality checks (`ceq`, `cne`, `weq`, `wne`) in `CombFolds.cpp`, specifically `applyCmpPredicate`, `applyCmpPredicateToEqualOperands`, and `ICmpOp::canonicalize`. These might just...
In order to support partial lowerings involving the FIRRTL dialect, and to mix in foreign operations and types, we need a way to pass foreign types through FIRRTL modules, instances,...
The current version of `HWMemSimImpl` implements read latency by inserting pipeline registers into the address and enable lines, which delays the time until the underlying data array is probed for...
Remove the `-mem` suffix in the `ignore-read-enable-mem` option of the `HWMemSimImpl` pass. "Read enable" should be unambiguous already. Note that this does not change the corresponding firtool flag, so no...
Add an interface for dialects and operations to provide reduction patterns. As a first step these should probably be just simple lists of reduction patterns, but at a later point...
As discussed in #1591, it would make sense to have `circt-reduce` provide a few default testers that cover the main things people want to check for in tool output: specific...
Consider the following FIR: ```python circuit Foo : module Foo : input a: UInt output b: UInt wire c: SInt wire d: UInt wire e: UInt c
In the CIRCT project we [came across an issue](https://github.com/llvm/circt/issues/1137) in how inferred widths differ between using temporary wires and using a node to construct a temporary value. In the discussion,...
In some cases we would like to emit `array_get` operations in SV with additional vendor pragmas, like `cadence map_to_mux` and `synopsys infer_mux_override`. This comes up in the FIRRTL dialect when...
PR #3404 introduced the emission of pragmas alongside multiplexer results: ```scala circuit MultibitMux: module MultibitMux : input a : UInt[3] input sel : UInt output b : UInt b