Fabian Schuiki

icon indicating a website link https://fabian.schuiki.ch

icon company SiFive icon location Silicon Valley, California icon location Senior Staff Compiler Engineer

Results 315 comments of Fabian Schuiki

Add logic type

Looks like a good start. How do the variants relate to `UX01ZWLH-`? Is something like the following correct? ``` U = Logic::U X = Logic::X 0 = Logic::Sd(false) 1 =...

Add logic type

Looks good :+1:!

Add logic type

Cool this is very nice!

Add MLIR input/output

@maerhart is working on this in his own fork right now.

Add MLIR input/output

MLIR output added as part of #134.

Formal Verification Support

The current strategy is to have assert/assume/cover be LLHD intrinsics: ``` call void @llhd.assert(i1 %some_condition); call void @llhd.assume(i1 %some_condition); call void @llhd.cover(i1 %some_condition); ``` These are not yet emitted by...

Add FIRRTL input/output

Excellent resource, thanks!

Joining the forces?

I think it would be a great idea to join forces in this regard! Your list of points on what such an IR HDL would need pretty much matches up...

LLHD-Sim reg primitive not implemented

Thanks for pointing this out! Added to the list of todos for version 0.15.

Add Yosys's RTLIL input/output

This is an excellent suggestion, especially since it helps to tie in LLHD with the existing ecosystem. Adding this to the planned v0.14 features. Some links for impl. reference: -...