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Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.

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Most CLE bits are documented, however there is at least 1 bit that is not documented, and 1 case that is not understood. Undocumented bits: - LCLKINV bit is not...

Synced local file(s) with [SymbiFlow/symbiflow-common-config](https://github.com/SymbiFlow/symbiflow-common-config). Changed files Created local CODE_OF_CONDUCT.md from remote CODE_OF_CONDUCT.mdSynced local CONTRIBUTING.md with remote CONTRIBUTING.md --- This PR was created automatically by the [repo-file-sync-action](https://github.com/BetaHuhn/repo-file-sync-action) workflow run [#1816994638](https://github.com/SymbiFlow/symbiflow-common-config/actions/runs/1816994638)

I have an XCVU33P on a board which allows it to draw a lot of power (6x20A of 0.85V to VCCINT), and would like to help.

This PR adds support for US architecture based on the KU035 part.

It is my understanding that Antmicro want to support the KCU105 dev boards. * [KCU104](https://www.xilinx.com/products/boards-and-kits/kcu105.html) - XCKU040-2FFVA1156E FPGA

It is my understanding that Antmicro want to support the ZCU10[45] dev boards. * [ZCU104](https://www.xilinx.com/products/boards-and-kits/zcu104.html) - Zynq UltraScale+ XCZU7EV-2FFVC1156 MPSoC * [ZCU102](https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html) - Zynq UltraScale+ XCZU9EG-2FFVB1156 MPSoC

Currently when using the bitread tool, the architecture defaults to the 7 series. When a bitstream is given of a different architecture such as Ultra Scale, this is the error...

> daveshah: UltraScale+ devices have all unused LUTs set to output 1 by default, to save power > daveshah: this results in loads of extra set bits in the FASM...

enhancement

The data for RCLK_XIPHY_OUTER_RIGHT is missing the bits for the pips that select the clocks going out to the XIPHYs: ![Screenshot from 2020-07-22 14-46-39](https://user-images.githubusercontent.com/5521177/88184192-4ebe2b80-cc2a-11ea-949c-b152277dd877.png) This isn't a massive blocker at...

Example: ``` 2020-07-20T19:40:10 - xczu3eg-sfvc784-1-e/060-rclk-seed - 3h01m: ERROR: [DRC RTSTAT-6] Partial route conflicts: 2 net(s) have a partial conflict. The problem bus(es) and/or net(s) are clk_IBUF[4]_inst/O, GLOBAL_LOGIC1. 2020-07-20T19:40:10 - xczu3eg-sfvc784-1-e/060-rclk-seed...