AXI BResp and RResp

[stridge-cruxml]

Instead of always returning ok, if trying to write to a read only address, or read a write only, or have a bad address return an error instead.

[esynr3z]

It's a very good proposal! However, from my experience and feedback I've earned - always ok is used in 99% of subordinate devices. It's very easy and cheap in terms of area/performance/power and very little requesters can handle those error responses.

So, I don't see any support of this in near future (at least by me). Sorry =(

[stridge-cruxml]

all good. I might have a go at some point. But it sounds like you desire this feature to be optional? Add a parameter to verilog generation class with something like enable_axi_response?

[iDoka]

+1 I think verilog parameter or define is reasonable solution for it.

[arnfol]

While I am not expecting this issue would be resolved soon-ish, while digging templates I found a possible workaround. This feature is not well-documented, but for Verilog and VHDL generators you can define read_filler in the config file. Setting it to some meaningful value like 0xDEADC0DE will give you the opportunity to debug if you are trying to read a bad address.

[arnfol]

I was wrong about not being well-documented: here