x-heep
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esl-epfl
eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
By default, the yosyshq uses the freq CLK/2 as SPI CLK. On an FPGA synthesized at 20MHz, the SPI_CLK is 10MHz, etc. When targeting ASICs, the SPI CLK may be...
Theoretically, the core is not using that value, still, it ASSERTS that the value is X and it is used in CSR or BRANCHES. To be checked. To see the...
Design a RISC-V CLINT (interrupt controller) to provide inputs to fast interrupts. Can be adapted from: https://github.com/pulp-platform/snitch/tree/master/hw/ip/clint
https://github.com/esl-epfl/x-heep/blob/main/sw/linker/link_flash_load.ld.tpl#L182 should be KEEP(...)
While going through the X-HEEP ASIC flow I can't seem to run the openroad-sky130 target and get GDS out. I have OpenROAD installed globally on my machine, oss cad suite...
