tapasco-riscv
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esa-tu-darmstadt
RISC-V soft-core PEs for TaPaSCo
## What this MR do? Update the setup of `swerv` to work with the renaming of the repository [`Cores-VeeR-EH1`](https://github.com/chipsalliance/Cores-VeeR-EH1). This solve #29 ## Summary of changes: - Change `swerv` to...
Hi all, The rule `swerv_setup` is no longer working with the core [Cores-VeeR-EH1](https://github.com/chipsalliance/Cores-VeeR-EH1) (previous SweRV). I saw that there is a fork of this core with the rule `swerv_eh2_setup`. This...
fill the info about the module you want to connect into common/module_info.tcl and add the parameter ADD_MODULE=true
Verbose log from OpenOCD: ``` Debug: 3454420 26428 riscv-013.c:2824 mem_should_skip_progbuf(): Skipping mem write via progbuf - insufficient progbuf size. Debug: 3454421 26428 riscv-013.c:2864 mem_should_skip_sysbus(): Skipping mem write via system bus...
This adds the picolibc support to the repository. The library is build automatically with a script calling make picolibc. Also software and hardware (controller) implementation is provided to support stdin/stdout...
