Erhan Kurubas

Hi @JanMatCodasip, is this PR OK for you? Anything from my side? @timsifive can you also please have a look?

> As for resets triggered outside of OpenOCD - I do not know how to best handle them, or if there is a reliable enough solution. In this case, we...

Hi Tim, I would like to implement this feature. As a summary; we need to handle 2 reset scenarios; 1- OpenOCD resets; as @JanMatCodasip suggested, it can be handled in...

@TheButlah Did you try with the correct cfg file as Roland mentioned. `board/esp32c3-builtin.cfg`

> Might also be worth considering using spdlog for logging Just a basic example of `spdlog` on esp-idf. https://github.com/erhankur/esp32-spdlog

@m-scasserra Thanks for reporting the issue and possible solution. I can confirm, your analysis is correct. I will provide a fix soon.

@m-scasserra I already have an internal MR for the small fixes. I added this fix also. It will be merged after the review.

There is no init log for the coredump. If coredump config is enabled, we should see `esp_core_dump_flash: Init core dump to flash` after `__esp_system_init_fn_init_components0` What is your IDF version? I...

@newsy5 Can you run openocd with -d3 option to see the verbose debug logs? Until now, I didn't connect any arm chip to the bridge. I will try to test...

Sorry, couldn't test it yet with the arm board. Can I ask for one more debug? Please add the below lines to your config file and send me the log.txt...