Epsilon

Simulating Arty A7 35 example in Vivado causes error due to hack in ibex_if_stage.sv

2

## Observed Behavior When I try to simulate the Arty A7-35 example in Vivado, I get an error message in elaborate.log: ERROR: [XSIM 43-3409] Failed to compile generated C file...

During bring-up of riscv-dbg on my Verilator testbench I found that TRST was asserted after running the dm_debug.cfg openocd script. A bit of investigation showed that TRST got asserted by...

Hi, I'm integrating LiteDRAM as a standard core into my SoC ([https://github.com/epsilon537/boxlambda/](https://github.com/epsilon537/boxlambda/)). I'm using function *sdram_init()* to initialize SDRAM. This function is not part of the litedram repository, however. It's...

Wishbone, 2 writes followed by colliding read returns incorrect result, write stuck in FIFO

2

I'm investigating an issue where a specific write-write-read sequence returns an incorrect result. My LiteDRAM core is configured for Arty A7 with a 32-bit wishbone port. I was able to...