litedram

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- use `bump2version` instead of raw `git tag` to both change code and git tag, when `.bumpversion.cfg` file is present in dependencies - cleanup develop extras in setup.py, was a...

timkpaine

DE10-Lite board litex boot with sdram enabled fails on memory read/write test `litex> __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> <...

LearnShareAlways

Hey! I would like to modify the configuration of my DRAM controller to increase the access time. Naturally, my first thought is to lower the DRAM input frequency (let us...

denishoornaert

Hi I have generated the code as in issue #344, I issued a write command on the wishbone interface, then a read command to the same location. I got read...

dinaabdelbaky

LiteDRAM DDR3 Core targeting Arty AXI read data appears on the Native port instead.

1

Hi, I have generated LiteDRAM core targeting DDR3 with the configuration in Fig1. I have noticed for a read command issued from the AXI interface the rd_data is returned in...

dinaabdelbaky

Carrying out the LiteDRAM standalone core initialization manually, through wishbone ctrl interface

5

 Hi, I am new to the liteDRAM. I generated the core in a standalone mode, targeting Artix device, I also generated the corr. csv containing the csr addresses. I...

dinaabdelbaky

Is it possible to adjust burst-length in order to widen data path ? Specifically, I would like to widen the data port of the DDR2 controller used with NexysA7 (aka...

fontamsoc

I am successfully using litedram_core on OrangeCrab02-25F when user_ports is wishbone, however when user_ports is native, liblitedram fails to initialize the controller through its wb_ctrl ports. Here is litedram_core generated...

fontamsoc

Hello, I use the LiteDRAMDMAWriter module of Litedram.dma . I have a problem, I would like to transmit data acquired in hard and write them in my ram without going...

Prigana

Closes #334 As far as I can tell, the axi port generation also assumes size 3, so hopefully this is the right fix

TheZoq2