Underclocking DRAM controler to increase access time

[denishoornaert]

Hey!

I would like to modify the configuration of my DRAM controller to increase the access time. Naturally, my first thought is to lower the DRAM input frequency (let us say in genesys2 litex-board) or the amount of phases.

I wonder if I can safely do one of the two. And, if yes, can I simply divide the input frequency while keeping the frequency of the softcore (e.g., VexRiscxv) unchanged?

Thanks a lot!