litedram

litedram copied to clipboard

Upconverter rewrite

4

This series of commits improve frontend adapter bandwidth.

mtdudek

QuarterRateGENSDRPHY

2

I'm trying to implement a Quarter-rate Generic SDR PHY module so that I can run a CPU at 40MHz with the SDRAM at 160MHz. It looked straight-forward at first but...

machdyne

Add support for Etron RPC DRAM

7

We should be able to add support for [RPC DRAM](https://etronamerica.com/products/rpc-dram/) in LiteDRAM. RPC DRAM reduces DDR3 pin count by removing all the command/address lines, data mask and CKE, ODT pins....

jedrzejboczar

Why are CL and CWL not included as speedgrade parameters in the module class?

1

Hello, I've defined several module classes for different DDR4 DIMMs. I've noticed that not all speedgrade-relevant timing parameters are included in the `speedgrade_timings` field of the `DDR4Module` class. For example,...

jaccharrison

LiteDRAM USPDDRPHY unable to meet DDR4 timing requirements?

8

Hi there, I've been working with AntMicro's Rowhammer tester on a ZCU104 development board. This framework instantiates a DDR4 PHY with a clock frequency of 500 MHz. I was not...

jaccharrison

ECP5: Use ODDRX1F for address and command bus

8

It should be possible to use ODDRX1F instead of ODDRX2F for the address and command bus, so that these signals can be placed on the top IO bank instead of...

kingoflolz

Figure out how to hook LiteDRAM to the WDDR PHY

1

@waviousllc recently released an [DDR PHY under an Apache 2.0 license](https://github.com/waviousllc/wav-lpddr-hw). The PHY is currently being used with proprietary memory controllers and it would be awesome to see it work...

mithro

Help generating DDR3 Verilog module for Digilent NexysVideo Artix-7 FPGA

3

I have had no luck generating a working DDR3 Verilog module for Digilent NexysVideo Artix-7 FPGA using: ``` { # General ------------------------------------------------------------------ "speedgrade": -1, # FPGA speedgrade "cpu": "None", #...

tambewilliam

Add support for DDR3 in MAX10

5

Currently the MAX10 FPGA is supported on some boards (e.g. DE10 Lite), but they all use SDR memory & the GENSDRPHY in litedram. Some cheap yet full-featured boards like the...

rdolbeau

Why is my simulation different to my target in regard to "address endianness"?

1

This is probably more of a "support" question. :S # Background I am trying to learn how I can stream data from sdram to something else, probably running at a...

nickoe