Evgeniy Naydanov

Wrtiting `zero` on RISC-V Debug Spec v0.11 changes it's cached value. Please see comments on how to fix it: * https://github.com/riscv-collab/riscv-openocd/pull/1044#discussion_r1629547981 * https://github.com/riscv-collab/riscv-openocd/pull/1044#discussion_r1629550393 This functionality (non-zero write to `zero`) should...

Tracking RISC-V Debug Spec v0.11 testing

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This issue is intended to track passrate of `riscv-tests/debug` testsuite on SiFive HiFive1 A01 | Version | Report | | ---------- | --------- | | e51f8695ed886f9d84cd7a71408822bfb800ac40 | https://github.com/riscv-collab/riscv-openocd/issues/1063#issuecomment-2080149946 |

Q extension support

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Currently RISC-V OpenOCD does not support RISC-V Q extension targets.

Currently, OpenOCD uses a chain of `lt` & `ge` triggers to set watchpoints (one of the options). However, in case the watchpoint is on the last address the strategy should...

Related to #1025. When a DMI read result is decoded, the current code assumes that the hardware provides the read address in the dmi.address field when returning the dmi.data. That...

There is no need to change if `dcsr.ebreak*` fields after a reset if a user requested a configuration that will result `dcsr.ebreak*` field values equal to reset values. Change-Id: I2844d30aef8f735c7b37394ee422e9b3f04a2e3b

Drop the use of `-coreid` in RISC-V targets

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Currently `-coreid` is used in RISC-V targets as `hartid`. https://github.com/riscv-collab/riscv-openocd/blob/a4020f1a0207dc218812ee262ce861d81aa7962f/src/target/riscv/riscv-013.c#L1909 This is misleading. (`hartid` name is probably not the best. Here it's used just as an example.) 1. ~By default...

https://github.com/riscv-collab/riscv-openocd/blob/3bed4c8015b319b97e6651a383db9ae001f11aa9/src/target/riscv/batch.h#L48-L55 The reason for making `RISCV_SCAN_DELAY_MAX` `INT_MAX / 2` no longer holds -- `jtag_add_runtest()` accepts an `unsigned int` since 0847a4d7fb9809a9bb36ba0965f43cb9d43ca2f3. https://github.com/riscv-collab/riscv-openocd/blob/3bed4c8015b319b97e6651a383db9ae001f11aa9/src/jtag/core.c#L592 This makes it possible to increase `RISCV_SCAN_DELAY_MAX` and remove/simplify...

See [#1115](https://github.com/riscv-collab/riscv-openocd/pull/1115#issuecomment-2325629261) for details.

There are cases when WPs disabled by `disable_triggers()` can not be re-enabled by `enable_triggers()`.

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Currently, `disable_triggers()` just goes through all the WPs and disables them one-by-one (the case when `r->manual_hwbp_set` is `false`): https://github.com/riscv-collab/riscv-openocd/blob/5afed58fcdb67ff87842dad9c3ab7f73ca0c8cd8/src/target/riscv/riscv.c#L2487-L2499 `enable_triggers()` works accordingly: https://github.com/riscv-collab/riscv-openocd/blob/5afed58fcdb67ff87842dad9c3ab7f73ca0c8cd8/src/target/riscv/riscv.c#L2526-L2536 Now consider the following situation: * A...