Emin Fedar

5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.

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Simple thread-based asynchronous TCP & UDP Socket classes in C++.

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5-Stage Pipelined RV32I RISC-V Core design in Verilog-2005. It has 32 GPIO pins and it is FPGA synthesible.

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Rust dilini en temelden basit örneklerle anlatan, derslerde kullanılmak üzere hazırlanmış açık kaynak slaytlardır.

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RISC-V RV32IM cpu circuit in Logisim Evolution.

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a Qt-Based Prayer Times application for Win/Linux/Mac

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a Cross-Platform Widget Management App. (Win/Linux/Mac)

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Rust & GTK4 version of Vakt-i Salah (Prayer Times) Application

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