embed-me

Undefined initial signals propagate to the UUT. Simple checks like "check_not_unknown" will fail. Other master modules (eg. [ram_master](https://github.com/VUnit/vunit/blob/master/vunit/vhdl/verification_components/src/ram_master.vhd), [axi_stream_master](https://github.com/VUnit/vunit/blob/master/vunit/vhdl/verification_components/src/axi_stream_master.vhd),...) all have their output values defined, so I still think it...

In general, this makes sense of course, however, the enable port for blk-mem is optional (at least for Xilinx, but I think also for Altera/Intel). If you do not use...

+1

I also used the zybo-zynq7 machine, 2020.1 and zeus as a starting point for a custom board development. Run into the same issue, however, adding CONFIG_OF_EMBED=y to the corresponding u-boot...