Kevin Laeufer

I still think this should be part of Chisel and not firrtl. Generally I would prefer if chisel users never need to import things from the firrtl package. The firrtl...

@sequencer could you share some of your use cases with us? Is this only for interfacing with Verilator from Scala or also from C++? I am playing around with a...

> @ekiwi any pointers on how to tackle this? Using no-dedup is the way? This seems to be a bug, but I do not understand enough about how annotations are...

One question that I think needs to be answered here is: What is the desired behavior for the toplevel (aka main) module? - prefix toplevel module - do not prefix...

@kenzhang82 Could you please run `sbt scalafmtAll` and commit + push any changes? The CI is complaining that the code isn't properly formatted.

> And done, can you check if it is roughly ok now? Sorry I don't have time yet to amend the PR, do you think we should merge this in...

That is a good idea! The SMT/Btor backend already does that: https://github.com/chipsalliance/firrtl/blob/1ddb492ea3a5d5a817d8782dac229169adbc1153/src/main/scala/firrtl/backends/experimental/smt/SMTEmitter.scala#L40

I think Jack wants to hold off on this since upgrading `protobuf-java` might also require a newer version of `protoc` to be available on user's computers.

> It should be noted that synthesizing and running the hardware on an FPGA board works as expected. Also, we assign signals in the harness like so: > `c->Patmos__DOT__cores_0__DOT__fetch__DOT__pcNext =...

Is there a reason why you changed from writing to e.g. `relBaseNext` to `relBaseReg` in [this commit](https://github.com/t-crest/patmos/commit/b2d8a38039b7d82931c02893b0aaac7b757f34ac)? Looking at your Chisel, it seems like the `Next` version if each signal...