Add Compiler Build Information to Output Verilog

[seldridge]

When emitting Verilog it would be useful to also include information about what version of the Scala FIRRTL Compiler generated it. This will help with users providing bug reports and avoid confusion about what Verilog was generated with the Scala FIRRTL Compiler vs. an alternative FIRRTL compiler.

h/t @rpadler

[ekiwi]

That is a good idea! The SMT/Btor backend already does that: https://github.com/chipsalliance/firrtl/blob/1ddb492ea3a5d5a817d8782dac229169adbc1153/src/main/scala/firrtl/backends/experimental/smt/SMTEmitter.scala#L40