egorxe

> this would be great for me too, as I'm trying to get 450 small designs into the area and so I need a much finer PDN. With all 4...

> You should look at #1109 #1109 is about power rings order and this issue is about separate control for rings and straps. They are related, but not the same.

Commit: 5f7ae00ed32778228cfbc41ecc772cf1214c8baf.

I also would like to note that deletion of some absolutely unrelated GDS parts (even millimeters apart from DRC errors) made errors vanish.

Thank you very much for your analysis and superb piece of open silicon software! I'm very sorry for making you sleep deprived, I was not anticipating you to react so...

> So maybe you can try with the DRC from https://github.com/efabless/globalfoundries-pdk-libs-gf180mcu_fd_pr? These rules produce same result on my design in flat and deep mode. So it seems that substituting ```drc(...

>Can you share the video file ? I've actually tried several and all of them played relatively fine. But I have no sound device, so not sure if it will...

BTW 4 cores also work without issues, but such config rarely achieves decent timings for my fpga with 175MHz system clock. With 4 cores@175MHz and 2G RAM even firefox becomes...

>I was thinking more about a fully hardware solution, where the cache periodicaly scrub itself from dirty cache lines. Is there a reason to do it besides framebuffer? For fb...

Same here https://platform.efabless.com/projects/1637 . Precheck passes locally with latest KLayout but OOMs on platform during FEOL CO.6a.