eddieh-xlnx

Test for issue found in #1019 by @Licheng-Guo

Node.getAllWiresInNode() returns empty list when Vivado doesn't

2

``` link_design -part xcau10p-ubva368-2-i; llength [get_wires -of [get_nodes INT_IBRK_FSR2IO_X0Y140/IO_TO_CTR_FT0_3]] ``` returns 22 wires. However, the testcase in this PR returns no wires.

Max delay timings for the following UltraScale+ resources, as described initially by [Maidee et al. -- An Open-source Lightweight Timing Model for RapidWright](http://www.rapidwright.io/docs/_downloads/FPT19-TimingModel.pdf) and subsequently implemented in RapidWright: 1. PIPs...

Currently fails verification due to #1002.

[DesignTools] makeBlackbox() to use phys netlist not logical

3

Currently, `makeBlackbox()` leverages the `EDIFNetlist` to find all leaf cells inside a particular point of the hierarchy. In the case of encrypted or detached netlists, this is not possible. Instead,...

1. Adjust wire base costs such that: i. A `NODE_SINGLE`/`NODE_DOUBLE` can (typically) no longer lead to a lower total path cost than the `NODE_LOCAL` that feeds it, even if it...

Add `YosysTools` convenience class to use [Yosys](https://github.com/YosysHQ/Yosys) for synthesizing Verilog files into RapidWright `EDIFNetlist` objects. Requires that the `yosys` binary be available on `PATH`. Currently, only a number of `synthXilinx`...

- `RouteNode` reduced from 80 bytes to 64 bytes - `RouteNodeGraph.{preservedMap,nodesMap}` (no longer `ConcurrentHashMap`-s) values' to be arrays to be sized no larger than number of base wires of its...