Ekansh Gupta

Create Verilog.md

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Created Verilog Informative Page. Operators.png yet to be merged with the master. Kindly adjust its order in the Interactive book A meaningful title for PR, not like: made changes to...

Edit contents of the Interactive book

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Circuitverse's Interactive book should be free of plagiarism. By replicating the content used by Tutorialpoint and Javatpoint is unethical and breaks the CoC of those platforms. Issue is created to...

Verilog Operators

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A meaningful title for PR, not like: made changes to xyz.md Fixes # Ref # #### Changes done: - [x] Task 1 #### Screenshots #### Preview Link(s): #### ✅️ By...

Verilog Programming Language Introduction and Adding Verilog for every Sub-Circuit.

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## Is your feature request related to a problem? Please describe. Being an EE undergraduate student, I'm always on the lookout for the simulation of Digital Electronics and their programming...

Updated Verilog Codes for Multiplexers

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A meaningful title for PR, not like: made changes to xyz.md Fixes # Ref # #### Changes done: - [x] Task 1 #### Screenshots #### Preview Link(s): #### ✅️ By...

Updated Readme

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Fixes # #### Checklist - [x] I have read the [Contribution Guide] and my PR follows them. - [ ] My branch is up-to-date with the master branch. - [...

Updated Indentation

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Fixes # #### Checklist - [ ] I have read the [Contribution Guide] and my PR follows them. - [x] My branch is up-to-date with the master branch. - [...

./run.py --billing default ekanshgReport ekanshg/cur % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 100 1555M 100 1555M 0 0 10.8M...